Testing of VLSI circuits are normally a tedious process due to the test data volume. It leads to extra power dissipation along with minimum fault coverage. This project presents a test data volume (TDV) reduction method for designs utilizing extremely high compression configurations, and it enables reducing the pin count interfacing with the Automatic Test Equipment. Based on the encoding requirements for every test cube, the proposed test compression method changes the number of shift cycles used to load the test stimuli dynamically. No additional pins or modification of the existing scan chains is needed, making the proposed method work with standard benchmark sequential circuits. A modification is proposed to reduce the test access time, that is single cycle access with hold mode and single cycle access without hold mode. Instead of a long scan chain, if each of the scan cells are tested separately in a single clock will reduce the access time and hence the effective testing time of sequential circuits.